Die Products Standards: Existing
Standards Contents
- JESD 49 - Procurement Standard for Known Good Die (KGD)
- J-STD-12 - Implementation of Flip Chip and Chip Scale Technology
- J-STD-26 - Semiconductor Design Standard for Flip Chip Applications
- J-STD-28 - Performance Standard for Construction of Flip Chip and Chip Scale Bumps
- EDR-4703 - Quality assurance guidelines for bare die including KGD
- ES 59008 - Data requirements for semiconductor die
- IEC 62258 - Semiconductor Die Products: Requirements for Procurement and Use
JESD 49 Procurement Standard for Known Good Die (KGD)
This standard was created to facilitate the procurement and use of high reliability
semiconductor microcircuits or discrete devices provided in bare die form. It provides
requirements and guidance to bare die suppliers for as-delivered performance, quality and
long-term reliability expected of this product type. It also reflects the special needs of
KGD product customers in terms of design and application data. It stresses that cooperation
between suppliers and users is essential.
This standard is seen in the industry as primarily a guideline that gives users a checklist
of issues to be addressed in the transaction. It was drafted by a joint MCC/SEMATECH task
group of industry professionals and submitted to JEDEC for standardization. It was released
as a standard in 1996. This document is available from the JEDEC website:
www.jedec.org
J-STD-12 Implementation of Flip Chip and Chip Scale
Technology
This informative document describes the implementation of flip chip and related chip scale
semiconductor packaging technologies. The areas discussed include design considerations,
assembly processes, technology choices, and application and reliability data. Chip packaging
variations include flip chip, HDI, micro BGA, micro SMT and SLICC. Also provides general
information on implementing flip chip and chip scale technologies for creating multichip
modules, I/C cards, memory cards and very dense surface mount assemblies. This document was
developed by IPC, EIA, MCNC and Sematech in 1996. While it is not a "standard", per se, it
contains a short description of a number of flip chip and csp parameters that would benefit
from standardization. This document has been approved by the American National Standards
Institute (ANSI). This document is available from the IPC website:
www.ipc.org
J-STD-26 Semiconductor Design Standard for Flip
Chip Applications
This standard addresses semiconductor flip chip design requirements. It provides information
for using standard semiconductor substrates, materials, assembly and test methods with
established fabrication, bumping, test and handling practices. Electrical, thermal and
mechanical chip design parameters and methodologies are covered in the standard, as well as
the reliability aspects associated with these conditions and processes. The information
applies to all new designs as well as modifications of non-flip chip designs. The standard
was developed by IPC and EIA and released in August 1999. It has been approved by ANSI. This
document is available from the IPC website: www.ipc.org
J-STD-28 Performance Standard for Construction of
Flip Chip and Chip Scale Bumps
This standard establishes construction detail requirements for bumps and other terminal
structures used for Flip Chip and devices Chip Scale carriers. The specific standards for
different terminations are appropriately matched to a particular interconnection process and
include such diverse terminations as solder bumps, columns, non-melting stand-offs and
conductive polymer deposits. The document articulates a set of designations and expectations
for product performance for the manufacturer and the user of flip chip or chip scale devices.
Recommendations are provided to implement the best commercial practices and evolving process
improvements. The standard was developed by IPC and EIA and released in1999. It has been
approved by ANSI. This document is available from the IPC website:
www.ipc.org
EDR-4703, Quality assurance guidelines for bare die
including KGD
This guideline was developed by EIAJ's Technical Standardization committee on Semiconductor
Devices and published in 1999. This is more a guideline than a standard. It proposes 4 levels
of Known Good Die (KGD) depending on the test and inspection regime to which the device is
subjected. These include:
- Visual mechanical
- Electrical characteristics
- Early failure
- Long-term reliability
These parameters are used to specify 3 levels of quality and reliability for bar die assemblies depending on the amount of test and inspection performed. This document is available from the JEITA website: http://tsc.jeita.or.jp/eds/sdrsl.htm
ES 59008, Data requirements for semiconductor die
This European standard was developed to provide both the seller and user with a list of data
required for the implementation of a bare die solution. It provided multiple levels of
compliance based on a seller's willingness to disseminate the required data.
The specification defined the data requirements for bare die products as follows:
- product identity and traceability
- product data
- die mechanical information
- test, quality and reliability information
- handling, storage and mounting information
- thermal data and electrical simulation data.
This standard is a 12-part document that includes guidelines and good practice for companies in the die business in Europe. This standard was developed in response to the need for a way of presenting information in a standard way for inclusion in a database. The data could then be downloaded into CAD design stations to facilitate the layout and simulation of MCMs and hybrid circuits. This standard's several parts were adopted by CENELEC between 1999 and 2002. This document is available from the CENELEC website: http://www.cenelec.org
IEC 62558, Semiconductor Die Products: Requirements for Procurement and Use (currently at CDV stage in the IEC - it is expected to become a PAS in 2004).
The IEC standard will facilitate the production, supply and use of semiconductor die products, comprising:
- Wafers
- Singulated bare die
- Die and wafers with connection structures
- Minimally or partially encapsulated die.
The standard defines the minimum requirements for:
- Data uniquely relating to die products
- Handling, shipping and storage of die products
The following parts of the standards are available from the IEC Web site:
Semiconductor die products - Part 1: Requirements for procurement and use
Semiconductor die products - Part 2: Exchange data formats