KGD Myth #2: There is a unique "yield issue" associated with assemblies of bare die.
KGD Myths Contents
This myth originated with all the hype surrounding MCM's in the early 1990s. Once the euphoria had passed, practitioners discovered that the yield of assembled modules was related to the number of devices in the module and the defect levels associated with each device. This simple relationship holds for any assembly of components (without redundancy) that must all function correctly to provide the correct system function. For most packaged IC's, defect levels are so low that the yield loss for the assembly of them is of the same order as assembly defects, and so does not present a significant problem. The assembly yield has been approximated by:
Yass'y = 100 x Pn
Where P is the probability that the device meets the specification and n is the number of devices. This assumes that all devices have the same probability of correct functionality.
Figure 2: Plot of the number of devices with certain probabilities of being "good" vs the number of them in the assembly gives assembly yield. Notice that the probability of the device being "good" is (1 - defect level).
So, it is critical that the defect levels for all components be accounted for in the assembly yield calculation. I fact, there are a number of other factors that come into the calculation as well. The overall module yield can be ascertained by:
Yass'y = Ym x Ps x (Pi) q x Pw
Where:
Ym is defined below
Ps is probability of substrate being defect free
Pi is probability of die interconnects being defect free and their quantity Q
Pw is assembly workmanship
Assume different chip types:
Ym = 100[(Pa)a x (Pb)ß x (Pc)? x . . x (Pz)?]
Pa is the probability that part A is defect free, and "a" is the number of pieces of part A, etc.
Again, the probabilities of defect free is the same as 1- defect level.