System in Package Assembly
System in Package (SiP) Assembly Contents
Stacked Package
Stacked, or three-dimensional (3D), multichip packaging methodologies have recently become mainstream, high-volume techniques of choice in helping system designers restrain the size, weight, power consumption, and cost of small, portable, and wireless consumer devices. However, debate continues over the pros and cons of stacking bare chips versus pre-packaged ICs, and some chips are more easily stacked than others. At the extreme leading edge of the art, new methods are being developed for wafer-level stacking.
Stacked System-in-Package Enabling Technologies
- Design
- Wafer thinning
- Die attach control
- Low loop height wire bonding
- Thin and dense substrate
- High yield assembly process
- High quality die products
- Stress management
- Testing
Definitions
Stacked-Die Package
A package that combines several die vertically in a Chip Scale Package and electrically
interconnects them to form a single device. Also called an MCP (Multichip Package)
Stacked-Packages
A package that combines several csp packages vertically and electrically interconnects them
to form a single device.
SiP (System-in-Package)
A SiP is a package that combines all of the electronic components (digital ICS, analog ICs, RF ICs, passive components or other elements) needed to provide a system or subsystem in one package, essentially an alternative to an SoC.
Stacked SiP
A stacked SiP includes both stacked-die packages and stacked-package packages, along with heterogeneous devices.