| TITLE | AUTHORS | FORMAT | AVAILABILITY |
| A Wafer-Level Burn-in Technology Using the Contactor Controlled Thermal Expansion | Yoshiro Nakata,, et al, | Conference Paper | Print |
| Accelerated testing :statistical models, test plans and data analyses | Nelson, Wayne | Book | Print |
| AT&T Reliability Manual | David J. Klinger, et al, editors. | Book | Print |
| BGA to CSP to Flip chip - Manufacturing Issues | Caswell, Greg, and Partridge, Julian | Conference Paper | Print |
| Burn-in Effectiveness -- Theory and Measurement | Hance H. Huston, Michael Wood, Vincent M. DePalma. | Article | Unknown |
| Burn-in: An Engineering Approach to the Design and Analysis of Burn-in Procedures | Finn Jensen, Niels Erik Petersen | Book | Print |
| Chip On Board Technologies for Multichip Modules | John Lau | Book | Print |
| Chip scale package (CSP) : design, materials, processes, reliability, and applications | Lau, John H | Book | Print |
| Conceptual design of multichip modules and systems | Sandborn, Peter A. | Book | Print |
| Defect Induced Failure Mechanisms Accelerated By Environmental Stress Screening | B.R. Livesay | Report | Print |
| Defect Level as a Function of Fault Coverage | T.W. Williams & N.C. Brown | Article | Online, purchase required |
| Die Products: Ideal IC Packaging for Demanding Applications | Larry Gilg, DPC & Chris Windsor, Portelligent, Inc. | Article | Unknown |
| Diffusion of Innovations | Rogers, Everett M. | Book | Online, purchase required |
| Digital Hardware Testing | Rajsuman, Rochit. | Book | Print |
| Digital hardware testing :transistor-level fault modeling and testing | Rajsuman, Rochit | Book | Print |
| Digital Systems Testing and Testable Design | Abramovici, Miron | Book | Print |
| Environmental stress screening :its quantification, optimization and management | Kececioglu, Dimitri | Book | Print |
| Environmental Stress Screening and Related Stress Applications | C.E. (Neil) Mandel Jr | Report | Print |
| Facing the Headaches of Early Failures: A State-of-the-Art Review of Burn-In Decisions | Way Kuo, Yue Kuo. | Article | Unknown |
| Failure Mechanisms in Semiconductor Devices, 2nd edition | E.Ajith Amerasekera, Farid N. Najm. | Book | Print |
| Flip Chip Technologies | John Lau | Book | Print |
| High Yield Assembly of Multichip Modules through Known-Good IC's and Effective Test Strategies | John K. Hagge, Russell J. Wagner. | Article | Online, purchase required |
| Introduction to Mechanical Properties of Materials | Eisenstadt, Melvin M | Book | Print |
| Introduction to Semiconductor Device Yield Modeling | Ferris-Prabhu, A.V. | Book | Print |
| Known Good Die Selection Tradeoffs: A Cost Model | Murphy, CF | Conference Paper | Print |
| Known-Good Die for Stacked CSPs: It's Not Your Father's KGD Anymore! | Jerry Secrest | Article | Online, free |
| Low cost flip chip technologies for DCA, WLCSP, and PBGA assemblies | Lau, John H. | Book | Print |
| Microelectronics Manufacturing Diagnostics Handbook | Abraham H. Landzberg | Book | Print |
| Microvias: for low-cost, high-density interconnects | Lau, John H. | Book | Print |
| MOS VLSI Reliability and Yield Trends | Murray H. Woods. | Article | Unknown |
| Multichip Modules and Related Technologies | Gerald L. Ginsberg, Donald P. Schnorr. | Book | Print |
| Neighbor selection for variance reduction in Iddq and other parametric data. | W. Robert Daasch, et al. | Conference Paper | Print |
| New Burn-in Methodology Based on IC Attributes, Family IC Burn-in Data, and Failure Mechanism Analysis | Sut-Mui Tang. | Book | Print |
| Packaging Trends for Portable Applications: Multichip packaging usage is increasing in the portables world | Larry Gilg | Article | Online, purchase required |
| RFID handbook: radio-frequency identification fundamentals and applications | Finkenzeller, Klaus | Book | Print |
| Roark's Formulas for Stress and Strain | Roark, Raymond J. | Book | Print |
| Smart Card Handbook | Rankl, W. | Book | Online, purchase required |
| Solder joint reliability of BGA, CSP, flip chip, and fine pitch SMT assemblies | Lau, John H. | Book | Print |
| Solder... its fundamentals and usage | Barber, Clifford | Book | Print |
| Some Theory of Sampling | Deming, W. Edwards | Book | Print |
| Stacked Chip Scale Packages Reach Prime Time | Lee Smith | Article | Print |
| Stacked-die Packaging Technology Toolbox | Marcos Karnezos | Article | Print |
| Standards Provide Key To Progress | Larry Gilg and Jim Wolbert | Article | Online, free |
| Statistical Post-Processing at Wafersort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies | Robert Madge, et al. | Conference Paper | Print |
| Technical Bulletin - Flip Chip | Karl Suss | Report | Print |
| The Dawn of 3D Packaging as System-in-Package (SIP). | Morihiro Kada | Article | Print |
| The market research toolbox :a concise guide for beginners | McQuarrie, Edward F. | Book | Print |
| The Promise of Known Good Die Technologies | Barbara Vasquez, Scott Lindsey. | Conference Paper | Print |
| Wafer burn-in (WBI) Technology Applied for RAMs | Furuyama, T., et al. | Book | Print |
| Wafer Level Burn-in | Dennis R. Conti and Jody Van Horn | Article | Print |
| Wafer Level Chip Scale Packaging (WL-CSP); An Overview | Philip Garrou | Article | Print |
| Wafer-Level Defect-Based Testing Using Enhanced Voltage Stress and Statistical Test Data Evaluation | Minh Quach, et al. | Conference Paper | Print |
| Wafer-level Packaging and Test, Technologies and Trends | Larry Gilg, DPC | Article | Online, free |
| Wafer-Level vs. Singulated Die Burn-In and Test | Larry Gilg | Article | Print |
| Wafer-Level vs. Singulated Die Burn-In and Test - Why is bare die burn-in and test important? | Larry Gilg, DPC | Article | Online, free |
| Wire bonding in microelectronics :materials, processes, reliability, and yield | Harman, George G. | Book | Print |
