Flip Chip Assembly Overview
Flip Chip Assembly Contents
Flip Chip is a term used to describe the multiplicity of mounting technologies that orient the face of the die toward the interconnecting substrate. Although flip chip technology was inaugurated by IBM and Delco in the 1960’s , it is now poised to become the interconnection method of choice for many die devices.
Figure 1. Early IBM flip chip, the controlled collapse chip connection, better known as C4, has been used extensively at IBM since the 1960’s.
The low parasitic electrical elements introduced by the bumps presents the best interface to the board, the ability to place power and ground connections throughout the face of the die, the fact that this is, in general, a “gang” bonding technique, are all playing a role in the conversion of wirebond devices to flip chip.
Figure 2: Interconnect model showing typical parasitic inductance and capacitance for several different interconnection types. The low parasitic elements for solder bump interconnect is a driving force in adoption of this technology for high performance IC devices.
In addition to these advantages, one of the most important is the fact that the bonding pads are not required to be placed at the periphery of the die – and in fact, the preferred arrangement is an array configuration over the face of the die. Array I/O also improves power delivery, high speed performance and provides relaxed pitch for ease of die product assembly. Some of the technologies finding favor now are solder ball flip chip and adhesive flip chip. Figure 3 shows the impact of using area array pad configuration vs. peripheral configuration.
Figure 3: I/O capability of flip chip at today’s pitches vs. peripheral location of bond pads illustrates the much higher capability of flip chip to accommodate high pin count devices.
As IC feature sizes continue to shrink according to Moore’s Law, area array pad configuration can keep the device size from becoming I/O limited.